The present invention relates to the field of frequency generators and, in particular, to the generation of signals with frequencies that are rationally related to a given input signal frequency.
Frequency generation by integral division is well-known in the art. Generally a clock source provides an input clock signal to a down counter which is configured to generate an output pulse once every N input clock pulses. As a result, the output clock signal frequency (f.sub.o) is equal to the input clock signal frequency (f.sub.i) divided by N (i.e., f.sub.o =f.sub.i /N), where N is an integer. However, if a range of frequencies is required, this design approach limits the range of frequencies that can be produced from a given input clock signal due to the requirement that the input clock signal be an integral multiple of the output clock signal. Further, though a signal at any particular frequency can theoretically be generated by this method, in practice the generation of high frequency output signals is limited due to the higher frequency input signal that is required (i.e., an integral multiple of the output) which may be beyond the signal frequency range of current integrated circuit technology. As a consequence, the requirement that the input clock signal be an integral multiple of the output clock signal limits the range of output frequencies and can result in circuit designs of added expense and complexity.
As a result, those in the art have taught that it is possible to utilize an input clock signal that is not restricted to being an integral multiple of the output clock signal in order to provide a higher resolution, or range, of output frequencies. In general, the prior art teaches that an output signal frequency can be rationally related to an input signal frequency by: f.sub.o =f.sub.i ((P/2.sup.m)/Q), where P, m, and Q are integers, and P&lt;2.sup.m &lt;Q, and m&gt;0. Here the prior art instructs that the input signal frequency is first multiplied by the fraction P/2.sup.m, and then divided by a number Q. Nonetheless, because of the 1/2.sup.m term, this requires that the input clock signal rate be a power-of-two higher than the output signal frequency which can still impose high frequency signal requirements on circuit design.
Those in the art have worked to remove even this restriction by teaching it is possible to fractionally produce a signal frequency by performing an integer division of the input signal frequency, i.e., f.sub.i /N, and then deviating from this frequency by a fractional amount M. In particular, U.S. Pat. No. 4,837,721, issued June 6, 1989 to Carmichael et al., discloses a fractional divider where the power-of-two term is removed and the output signal frequency is related to the input signal frequency by: f.sub.o =f.sub.i /(N+M), where N is an integer and M is equal to 1/2. This approach fractionally divides the input clock signal frequency by periodically reversing the polarity of the input clock signal. However, since M is equal to 1/2, the denominator can only change in discrete fractional steps, which limits the amount of frequency resolution obtained. In comparison, U.S. Pat. No. 4,241,408, issued Dec. 23, 1980 to G. Gross, discloses a fractional divider where the output signal frequency is also related to the input signal frequency by: f.sub.o =f.sub.i /(N+M), and N is an integer, and M is a fraction equal to L/2.sup.K, where L and K are integers, and L&lt;2.sup.K. Nevertheless, though this improves the range of frequencies that are available, the output resolution is still restricted to fractional steps of l/2.sup.K.